Deposition processes are commonly used in semiconductor manufacturing to deposit a layer of material onto a substrate. Processing is also used to remove layers, defining features (e.g., etch), preparing layers (e.g., cleans), doping or other processes that do not require the formation of a layer on the substrate. Processes and process shall be used throughout the application to refer to these and other possible known processes used for semiconductor manufacturing and any reference to a specific process should be read in the context of these other possible processes. In addition, similar processing techniques may apply to the manufacture of integrated circuits (IC) semiconductor devices, flat panel displays, optoelectronics devices, data storage devices, magneto electronic devices, magneto optic devices, packaged devices, and the like. As feature sizes continue to shrink, improvements, whether in materials, unit processes, or process sequences, are continually being sought for the deposition processes. However, semiconductor companies conduct research and development (R&D) on full wafer processing through the use of split lots, as the deposition systems are designed to support this processing scheme. This approach has resulted in ever escalating R&D costs and the inability to conduct extensive experimentation in a timely and cost effective manner.
Simpler processing methods for simple device structures can be employed in R&D for large scale screening of materials and process conditions. For example, shadow mask deposition is well-known and has been used for years in microelectronics capacitor device fabrication for electrical testing of dielectrics. The shadow mask deposition process is much simpler and more cost effective than the other patterning process of photolithography.
To create a capacitor electrode pattern on a substrate, a shadow mask is placed over the substrate surface. The substrate with the shadow mask is then subjected to a deposition process of a conductive material. The substrate areas corresponding to the aperture openings of the shadow mask receive a deposition coating while other areas are shielded by the shadow mask. To achieve vertical deposition profiles, the shadow mask is preferably thin and forms intimate contact with the substrate surface during the deposition process.
One major limitation of shadow mask deposition process is the lack of sufficiently resolution to meet today's demands. For example, shadow mask processes with apertures smaller than 50 microns are difficult due to potential mask and deposition defects, together with probing difficulties. Large area electrodes fabricated with shadow mask processes can lead to high leakage current and low yield for thin dielectrics to obtain meaningful trends for optimization. This requires the use of dielectrics in a thicker range that is far away from production-worthy processes. As a result, costly photolithography manufacturing techniques continue to be utilized to produce such high resolution products.
Hence, there is a need to improve the resolutions of the devices fabricated with shadow masks without reducing the size of the shadow mask openings.